I currently have a new role for a senior level digital verification design engineer to join my clients expanding team in Prague. My client architect, design and deploy advanced technology mixed signal sensors and power devices.
You will be using cutting edge tools to verify state of the art products in my clients Model Based Design flow for digital signal processing applications. Knowledge of Universal Verification Methodology, SystemVerilog assertions and Cadence verification tools is the key knowhow. The role
Education and Experience Requirements
- Preparation of digital design test plan from requirements using Cadence
- Definition and creation of UVM-SV test environment, test plans, tests and functional coverage
- Verification of signal processing and control algorithms using Cadence and MathWorks tools
- Preparation and/or leading of verification reviews
- Modification and/or debug of Simulink models in mixed signal test environment
- Coordination of verification activities with abroad team members
- Cooperation with System Engineering team on Jama Requirements
You will possess a Bachelor's / Master’s degree of 5+ / 3+ years of experience in Digital Design and/or Verification.
- Excellent communication, documentation, problem-solving and analytical skills are required.
- Knowledge of SystemVerilog and UVM is a must.
- Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.
For a confidential discussion and further information please contact Rachel Mason at IC Resources.