NOW HIRING!! Senior Verification Engineer in the Capital of France…Paris! This is a superb opportunity to join my client a leading developer and provider of 5G and 4G chips and modules for IoT devices in the lively and cultural City of Paris.
I am looking for a Senior Verification engineer in a growing team responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology.
As part of the role, you will architect, develop & own blocks, sub-subsystem and system-level verification benches. As the successful engineer you will be a major contributor to advanced SV UVM methodologies and to infrastructure development.
You will be part of an advanced DV flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and VLSI design teams.
As the Senior Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and are expected to have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system. EXPERIENCES:
Note: You must have French working rights and be able to communicate in English.
- Must have B.Sc. / higher in Electrical Engineering / Computer Engineering / Computer Science from a well-known University
- Must have 5+ years of hands-on experience in ASIC verification using UVM System Verilog
- Must have experience in unit-level as well as subsystem/full-chip verification.
- Must have experience working on complex ASIC or SOC designs
- System-Level understanding
For more information and a detailed discussion please contact Rachel Mason at IC Resources.