For our client, a semiconductor leader in Munich, Germany we are looking for a Senior ASIC Verification Engineer (f/m).
For this technically challenging position as a Senior ASIC Verification Engineer we are looking for verification engineers with an experience in digital verification of at least 10-15 years. As a Senior ASIC Verification Engineer you will require solid knowledge of HW description languages like Verilog, SystemVerilog or similar, a university degree in Electrical Engineering or Electronics or equivalent and solid debugging skills and experience with UVM. For this position you also bring good C/C++ knowledge for verification.
In the position of a Senior ASIC Verification Engineer you will:
- develop verification solutions for ASICs
- carry out functional verification planning and develop test cases
- constantly improve the script environment
- develop prototyping solutions
- initiate the introduction of new tools
If this vacancy of a Senior ASIC Verification Engineer sounds appealing to you, please contact Nicole Lamprecht.