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UVM Verification Engineer, Graz


UVM Verification Engineer, Graz


Job ID: 167191
Location: Graz, Austria, Europe
Salary: €65+ per hour
Job Type: Contract
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Partially remote UVM Verification contract based in Graz.

Please see the spec below and contact Mitchell Carpenter at IC Resources for more detail

  Responsibilities
• Responsible for functional verification of RTL at block and SOC level under guidance as part of the verification team.
• Interface with design, software, architecture, and validation teams to understand application and function of design and define coverage goals to verify required function.
• Develop debug and maintain test code to meet coverage goals for the design models (RTL, Gate sims, Power aware sims, FPGA, Emulation platform) under guidance as part of the verification team.

Profile

Required:
• Degree/Masters in Electronic and or Computer Engineering
• Exposure to Hardware design, ability to read RTL code ( e.g. Verilog/System Verilog/ VHDL)
• Proficient in Object Oriented coding with experience developing and debugging software ( e.g. C/Java )
• Conceptual understanding of Components of a System on Chip system including CPUs, DMA, MMU, PLLS, RAM,ROM, Flash and peripheral interfaces.

Bonus:
• Understanding of digital IC design process.
• Understanding of software development process for embedded CPUs
• Exposure to Metric driven verification, directed and constrained random methodologies, functional and code coverage concepts.
• Experience in the use of EDA tools for IC development, simulation and debug (RTL simulators, C compilers, debuggers)


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