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UVM Verification Engineer, Sweden


UVM Verification Engineer, Sweden


Job ID: 167369
Location: Sweden, Europe
Salary: Competitive salary + visa + relocation
Job Type: Permanent


Join Sweden’s fastest-growing technology consulting firm as a Senior UVM Verification Engineer, and enjoy a high living standard, interesting work opportunities and a vibrant, friendly, working culture in Lund, Sweden. Visa sponsorship and relocation assistance can be provided.

Our client is looking for a Senior UVM Verification Engineer to join their rapidly growing team and take ownership of the Verification phase for ASICs within the wireless communications sector.

Here as the UVM Verification Engineer your role will include but not be limited to:
  • Creating design verification documentation and test plans
  • Implementing verification IP and test-benches
  • Creating coverage models
  • Testing and debugging in Verilog and SystemVerilog
  • Creating assertion-based models
You will need to have:
  • At least 8 years’ ASIC Verification experience
  • Strong skills in SystemVerilog and UVM
  • Very good scripting skills (either in Python, tcl or perl)
  • Excellent communication skills in English

Nice to haves:
  • A background within wireless telecoms (baseband / 5G) would be useful, but not essential
  • Any experience within high-speed interfaces such as Ethernet, again would be a benefit
Get in touch today for immediate consideration!

Contact Caroline Pye @ IC Resources


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