Chip finishing/Analog IC Layout Engineer
Bristol in the Southwest of the UK is offering a permanent position for an Analog IC Layout Engineer to join a design services company and support their design team in the layout of Analog/Mixed Signal IC's for a wide range of applications. This is an opportunity to join a core group of experienced Analog/Mixed Signal and Digital Design and Layout Engineers where you will be tasked with delivering quality layouts using Cadence tools in a range of geometries in a Cadence environment and using standard tools for parasitics (DRC, LVS) and be responsible for the finishing of the chip.
Proven experience in chip finishing is required for this position including DRC, ERC, ANT, LVS, seal ring and sensor layer introduction and all final database checks and documentation before submitting the chip to the fab.
The successful Analog IC Layout Engineer will have a minimum of 3 years of experience in Analog and Mixed Signal IC Layout in CMOS technology and Cadence as well as proven experience in chip finishing tasks.
Due to strict visa rules in the UK, only applicants with the preexisting right to work in the UK can be considered for this opportunity.Print Save To Shortlist