Work as Analog IC Layout Engineer on the layout of low power ICs for consumer applications from transistor through to block level Layout in different process nodes including parasitic extraction using LVS, ERC and DRC. You will work on the implementation and development of layout tools and processes and support Design Engineers and Physical Designers.
You are suited for this position as an Engineer with a Degree in electronic engineering and have several years of experience in Analog IC Layout in Cadence environment and good general knowledge in Semiconductor theory including transistors, resistors and capacitors.
For more information about this role and to apply please contact Ane@ IC Resources with your CV and a time for an initial call stating your time zone. Candidate from international locations can be considered.
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