Analog IC Layout/MPW Assembly Engineer
In this role at a leading Semiconductor supplier of low power Analog Mixed Signal IC's for applications used in a variety of markets from communication to automotive that has their own fab, you will be involved in IC physical development from layout, mask design to IC manufacturing, so you must be familiar with the layout flow using Cadence tools as well as the Mask Generation flow.
Your tasks will include the Layout of Analog IPs and complex Analog Mixed Signal IC's, utilization of advanced CAD tools for mask design, delivery of clean layout data for tape-out and mask generation.
Working closely with the Process Development and Process Control Teams, you will be responsible for the MPW Assembly including the collection of GDSII from the Business Units, Process Development and External companies, Layout of the frame and assembly, running verifications to ensure the Masks match the specifications.
The successful Analog IC Layout Engineer is industry degree qualified and has 3+ years of experience in Analog IC Layout (Cadence Virtuoso Layout XL and physical verification with DRC and LVS tools) and ideally some experience with SKILL, TCL or UNIX as well as knowledge of mask processing, device construction and fab processing. Knowledge of Calibre DRV and Mask Compose is an added benefit to your application. You must be familiar with layout flow using Cadence Open Access tools and also Mask Generation flow.
For information and to apply please contact Ane at IC Resources with your CV and a time for a call.