A Semiconductor company based in the Thames Valley and market leader in imaging applications is looking for an Analog IC Layout Engineer to support an experienced team to in the creation of layouts of Analog Mixed Signal IC's in Cadence and Mentor tools for modifications to existing products and develop layout solutions for new products.
Your responsibilities will include floorplanning, top level layout, top level verification (LVS, DRC, ERC), top level LPE.
You are the right candidate for this role if you are industry degree qualified and have at least 2 years of experience in Analog IC Layout from within a Semiconductor company. You have solid understanding of Analog IC Layout, Cadence Virtuoso, capacitive and inductive coupling, matching, verification and evaluation, floorplanning Analog Mixed Signal blocks. In addition you should be familiar with digital techniques such as P&R, timing driven layout, clock trees, EMIR, ESD and be able to insert blocks from these processes into Analog Mixed Signal IC Design.
Regarding any questions and to apply, please contact Ane at IC-Resources with your CV and a time for a call.
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