Are you an ASIC Deign Engineer or an FPGA Design Engineer with experience in RTL Design using Verilog or VHDL. If yes, we have an exciting new ASIC / FPGA Design role with a leading semiconductor company based in Dublin. As the ASIC / FPGA Design Engineer you will be working on RTL coding, integration, synthesis, verification and timing analysis on FPGA's for a variety of different applications.
This is a senior position so you will have at least 8 years experience in RTL design on either ASIC's or FPGA's and you will be able to relocate to Dublin on a permanent basis.
8 + ASIC / FPGA design experience
RTL design in Verilog / VHDL
Experience in integration, synthesis, verification and timing analysis
Permanent job in Dublin
If you could be interested in this role please contact Rob at IC Resources - firstname.lastname@example.org
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