Design Verification Engineers
€€€ Excellent package
Our client is making a significant investment in their Design Verification team, and have a number of positions open at all career levels to Principal Engineer.
To join a growing SOC Verification team within a world leader in the mobile industry.
The successful Design Verification Engineers will be high calibre, degree-qualified individuals with proven experience and exposure in a few of the following areas:
- Experience in design, testing and verification in hardware and software on SoCs and SoC subsystems.
- Methodologies for verifying complex units on SoC using industry standard tools and technologies
- Proficient in developing unit and SoC level test benches using OVM/UVM
- Constrained random functional verification environment in System Verilog
- Experience in Gate Level Simulation (GLS) verification flow for SoC verification.
- Experience of pre and post-silicon verification testflow and automated test benches
- Strong knowledge of test-plan generation, coverage analysis transaction level modelling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
- Verilog, C/C++, System C, Java, TCL/Perl/shell-scripting required
- Building and leading verification teams is a plus
- RTL design and front end design flow experience
This team is part of a long term commitment to the site, offering considerable opportunity of career growth and advancement.
Please contact Dave @ IC Resources for more information
Key words: Digital, IC, IP, SOC, Verification, Engineer, functional, formal, OVM, UVM, SystemVerilog, assertions, psl, test, random, wireless, CMOS, Semiconductor, Ireland, Europe.