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Digital Design Engineer (STA)

This is an exciting opportunity for a Digital ASIC Design engineer to join our client, a leading international semiconductor company who create cutting-edge solutions to improve the quality of life with green, easy-to-use products, and dedicated for more than 10 years in the memory interface technology.

This role is located in Shanghai. As the Digital ASIC Design Engineer (STA) you will be in a position within the sensor product design team. Responsibilities focus on developing and implementing architectures for IC products. This covers the complete range from an architectural concept all the way to the HDL implementation.

With their innovative proprietary technology processes, our client thrive on re-imagining and re-defining the possibilities of high-performance power solutions in industrial applications, telecom infrastructures, cloud computing, automotive, and consumer applications.

The role:

* Developing/Building SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow.
* Checking/Analysing SoC/IP level synthesis/timing analysis/formality check/CDC check.
* Co- working closely with time closure with P&R and deliver constraints.
* Coding block level RTL, and supporting other tasks from the team.

Qualifications:

* Experienced in digital design experience, especially in STA.
* Previous experience or strong knowledge in complex timing closure are good plus.
* Skilled in DC/PT/formality check tools.
* Be familiar with system coding, such as Tcl/Perl and others.
* Fluent communication in English and Chinese

For a confidential discussion please contact Nick Chen at IC Resources.

China

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Job Details
  • £28000 - £51000 per annum
  • Shanghai, China
  • Permanent
  • 158280_icr
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