We are currently working with a client based in Austria that are looking for a Digital IC Verification engineer who can assist them with a 6 month project starting in the next 2-3 weeks.
Applicants would need a working knowledge of SystemVerilog test benches within a UVM environments.
The ability to maintain an existing is the primary function of the position however experience with creating cover groups and developing an assertion based coverage plan would also be beneficial.
The client are open to discussing a portion of remote working however this would be negotiated after the initial 2-3 weeks ramping up on site.
If you are a digital verification engineer looking for a new project that will take you up to the summer please get in touch.
Applicants must have the eligibility to work in the UK to apply for this position due to the short nature of this project.
If this is of interest please get in touch: firstname.lastname@example.org
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