Are you an ASIC verification engineer bored of the same SystemVerilog UVM contracts and looking for a change?
I am currently working with a UK based client that are developing processors for primary audio applications. They are looking for an engineer to assist them with their verification team for an initial 6 months period starting in early 2019.
Instead of using mainstream SV/UVM principles for hardware verification they focus mainly on C and assembler models to complete the hardware verification of the processors.
Due to the urgent requirement of this project applicants must have existing eligibility to work in the UK.
If this position could be of interest then please get in touch: firstname.lastname@example.org
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