Digital ASIC Physical Design Engineer - Manchester
£££Competitive salary, plus benefits and excellent progression
This is a great opportunity for a Digital ASIC Physical Design Engineer join a fast growing, multinational organisation developing ICs for the space industry.
Working as a member of the Physical Design team, you will be responsible for:
· Physical implementation of block and chip level digital designs, including 3rd party IP block inclusion
· Full block level timing closure and signoff checks including power planning and analysis
· Working with the front-end RTL design team to develop timing constraints for implementation at the chip & block level.
· Place & Route activities
· Prior working experience within Digital Physical Design, with a good understanding of the RTL-GDSII flow
· Expertise within Synthesis, Floorplanning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) & Timing Closure
· Experience in either Cadence OR Synopsys tool suites
· First-rate communication skills in English
· Scripting skills in Tcl/Python/Perl would be ideal
You can expect an exciting, challenging role within a fast-growing business, with a lot of room for future growth and career development, as well as a competitive rewards package.
For more information or to apply, please contact Caroline Pye @ IC Resources.