Physical Design Team Lead
Our client seeks a Physical Design Team Lead to be the cornerstone of a new Physical Design team in Southern Ireland.
This is a rare and exciting opportunity for a Physical Design Team Lead to join a hugely successful global business and build a brand new Digital Physical Design team from scratch. This company is a world leader in wireless semiconductors and solutions that are used in huge volumes within handsets, tablets and consumer devices. With ongoing growth they are now looking to assemble a new backend design group, and are ideally looking to appoint the Physical Design Lead as the first hire.
The Physical Design Lead will be responsible for leading and implementing complete Back-End flow from netlist to Tapeout including, floorplanning, placement, CTS (Clock Tree Synthesis), timing optimization, routing, physical verification, formal verification and timing closure on state-of-the-art CMOS technologies (28nm, 20nm and 14nm) and designs. This is a highly technical role, which will involve leading, mentoring (and recruiting) Physical Design Engineers for the group.
The successful Physical Design Lead will be a high calibre, degree-qualified individual with proven experience and exposure in the following areas:
*10+ years hands on experience in physical design, with team leadership experience
*An in-depth understanding of the RTL-GDSII flow
*Experience with large SoC designs with frequencies >1GHz
*Familiar with typical SoC design issues such as multi-voltage and clock domains, Si based timing closure challenges
*Excellent communication and interpersonal skills; this role will involve working closely with teams in the US and India
This team is scheduled for long-term future growth; hence the Physical Lead will be the key figurehead for Physical Design at this site.
Please contact Caroline @ IC Resources for more information
Key words: Digital, Physical Design, Lead, Team Lead, ASIC, Backend, Physical Implementation, RTL, GDS2, GDSII, RTL-GDSII, floorplanning, Place & Route, routing, P&R, PnR, synthesis, clock tree, tapeout, timing closure, STA, static timing analysis, SoC, DFT, design for test, EDA, Synopsys, Cadence, clock tree synthesis, CTS, physical verification, netlist, CAD, CMOS, Semiconductor, Ireland, Europe.