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RF IC Layout Engineer

A growing multi-site start up business based in the Thames Valley is looking for an experienced RF IC Layout Engineer to support them in the development of RF chips for space applications.


The successful RF IC Layout Engineer will have at least 5 years of industry experience in Analog/RF IC Layout including experience in multiple RF IC blocks from initial stage to tapeout and strong understanding of the layout constraints, reliability requirements, tapeout sign off procedures for TSMC, SiGe or BiCMOS as well as Cadence and Matlab.


As RF IC Layout Engineer you will be responsible for the full chip layout, lead the layout implementation of the block and support post-extraction simulations as well as participate in top level integration and optimisation of the full chip.


For more information please contact Ane at IC Resources with your CV. Only candidate with the right to work in the UK can be considered (UK perm residence, citizen or EU national)

South East England

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Job Details
  • Reading, England
  • Permanent
  • JO-1905-138651_icr
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