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Senior Analog IC Layout Engineer

A London based Analog IC Layout opportunity for a very experienced and independently working professional with at least 4-5 years of post-graduation experience in Analog IC Layout is available at a Semiconductor company active in the sensor development for biomedical applications. This opportunity could be of particular interest for you if you have a background in medical device development and related legislation or an interest in moving into the biomedical field.

In your role as Analog IC Layout Engineer you will be responsible for the layout of individual circuit blocks in particular ADC's and PLL's. Working in a multi-disciplinary team of IC Design Engineers on innovative Analog Mixed Signal IC Layout in advanced process technologies, you will be responsible for the chip floor planning up to ESD, verification, tape out, and mask data verification (Cadence Virtuoso, Assura, DRC, LVS).

In addition you will manage the entire EDA flow with responsibility for keeping Cadence tools up-to-date and installing and maintaining foundry PDK's and be responsible for the team's tape-outs and liaison with the foundry.

You will work in very close collaboration with the IC design team, software development engineers, hardware development engineers, mechanical engineers as well as scientists and external development and manufacturing partners in the UK and abroad.

For more information and the full job spec please get in touch Ane at IC Resources today with your CV and a time that work for you for an initial call to discuss your questions and expectations.

Candidates from within the EU will be considered with priority.

Cambridgeshire, London, Norfolk, South East England, Suffolk

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