Senior Analog IC Layout Engineer
Munich, Southern Germany
Salary depending on experience
A multinational semiconductor company is looking for a Senior Analog IC Layout Engineer for their design centre in Southern Germany to technically lead a small team of Analog IC Layout engineers. In this position you will be working on the block level, macro and top level layout for high speed ADCs.
As the successful Senior Analog IC Layout Engineer you have several years of experience in Analog IC Layout in a Cadence environment at block and full chip level including floor planning ideally with high speed analog chips like ADCs, DACs or PLLs in process nodes below 28nm.
For more information and to apply please contact Ane at IC Resources with your CV!
You can search for a new job here.