Senior Digital Physical Design Engineer - Ireland
Opportunities like this don't come along often - we are looking for several Senior Physical Design Engineers for our client's brand new SoC team based in Cork.
This company is a global name in wireless semiconductors and solutions - their ICs are used in huge volumes within handsets, tablets and consumer devices. They are expanding internationally, and in Ireland are currently in the early stages of building a brand new Physical Design team from scratch. This is a chance to become one of the very first members of a SoC team set for big things, and enjoy working in a start-up style environment with the financial security of one of the world's biggest high-tech giants.
As a Senior Physical Design Engineer, your role will involve:
*Taking responsibility for the complete physical design flow for communication chipsets, enabling low power implementation methods
*working on the physical design execution and integration of the IP into the SoC
*Understanding the design in context of physical design timing closure including developing of timing constraints for implementation.
*Physical design timing closure.
*Developing new scripts/flows to improve the backend design flow.
Skills / experience required:
*A successful track record working in industry as a Physical Design Engineer for digital ASICs
*Strong knowledge of tools for physical design implementation in advanced technologies such as 28nm, 20nm and 14nm CMOS.
*In-depth knowledge of the entire physical design flow from RTL to GDS (including Floorplanning, Power planning, Place and Route (P&R) Clock Tree Synthesis (CTS), Post route optimization and DRC closure.
*Understanding of signal integrity and timing closure issues
*Skills using Perl and tcl
A Bachelor's / Master's degree in computer science, electronic engineering or related technical subject is also required.
Work permit sponsorship can be provided for candidates already based in the EU.
For details, please contact Caroline Pye @ IC Resources for a confidential discussion.
Key words: Digital, Physical Design, ASIC, Backend, Physical Implementation, RTL, GDS2, GDSII, RTL-GDSII, floorplanning, Place & Route, routing, P&R, PnR, synthesis, clock tree, tapeout, timing closure, STA, static timing analysis, SoC, DFT, design for test, EDA, Synopsys, Cadence, clock tree synthesis, CTS, physical verification, netlist, CAD, CMOS, Semiconductor, Ireland, Cork, Europe.
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