I am looking for a Senior/Principal Digital Physical Design Engineer to join my client's silicon team and drive physical implementation activity for complex ASICs and test chips for the satellite industry.
This is a great opportunity join a fast growing team within an established, international company. Based out of our client's expanding design centre in Manchester, here you'll play a leading technical role and be a key point of expertise for Physical Design, taking responsibility for:
· Physical implementation of block and chip level digital designs, including 3rd party IP block inclusion
· Full block level timing closure and signoff checks including power planning and analysis
· Working with the front-end RTL design team to develop timing constraints for implementation at the chip & block level.
· Insertion of DFT test structures and chip level integration
· Technically leading P&R (Place & Route) activities
· Established experience up to Principal level within Digital Physical Design, with experience across the full RTL-GDSII flow
· Expertise within Synthesis, Floorplanning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) & Timing Closure, Physical Verification, Power Analysis, Formal Verification and ATPG insertion/pattern generation
· Experience working in 32nm technology or below
· Solid experience in either Cadence OR Synopsys tool suites
· First-rate communication skills in English, with a natural ability to easily communication with design teams, 3rd part IP suppliers and EDA tool vendors to improve scripts and tool flow
You can expect an exciting, challenging role within a fast-growing business, with a lot of room for future growth and career development, as well as a competitive rewards package.
For more information or to apply, please contact Rachel Mason @ IC Resources.
Tel: +44 (0) 118 988 1107
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