{"id":104135,"date":"2026-04-16T00:00:00","date_gmt":"2026-04-15T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/design-verification-team-lead-mixed-signal-asic-444642\/"},"modified":"2026-07-24T18:07:33","modified_gmt":"2026-07-24T17:07:33","slug":"design-verification-team-lead-mixed-signal-asic-444642","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/design-verification-team-lead-mixed-signal-asic-444642\/","title":{"rendered":"Design Verification Team Lead (Mixed-Signal ASIC)"},"content":{"rendered":"<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">A leading global semiconductor company in Edinburgh UK (20,000+ employees, 30+ countries) is looking for a Design Verification Team Lead to drive verification on complex mixed-signal ASICs.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">This is an ideal step-up role for someone who\u2019s led a small team (2-3 engineers) and wants more ownership, without moving into heavy people management. The package is highly competitive, with a base salary up to \u00a390,000, plus bonus and RSUs on top.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong><span style=\"line-height: 115%\">The role<\/span><\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Lead and mentor a small verification team <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Define and execute verification strategy (UVM\/SystemVerilog) <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Oversee functional + formal verification <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Collaborate with design &amp; architecture teams <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Drive coverage, quality, and delivery <\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong><span style=\"line-height: 115%\">What you\u2019ll bring<\/span><\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Strong design verification background (digital or mixed-signal) <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Experience leading small teams or projects <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Skills in SystemVerilog, UVM, assertions, coverage <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Exposure to mixed-signal \/ ASIC environments (RNM a bonus) <\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong><span style=\"line-height: 115%\">Why join<\/span><\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\"><span style=\"line-height: 115%\">Work on globally deployed technology <\/span><\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\"><span style=\"line-height: 115%\">Clear path into technical leadership <\/span><\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\"><span style=\"line-height: 115%\">Relocation support available <\/span><\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\"><span style=\"line-height: 115%\">High-impact role in a growing, innovative business <\/span><\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong><span style=\"line-height: 115%\">Who this suits<\/span><\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Senior Engineers stepping into leadership <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Small team leads wanting more scope and visibility <\/span><\/li>\n<li><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Engineers open to relocation + global projects <\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">If you want influence, ownership, and real technical leadership (without becoming a full-time manager), this is a strong move.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;line-height: 115%;font-family: Verdana\">Interested? Contact me directly \u2013 Steph Hutchinson<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>A leading global semiconductor company in Edinburgh UK (20,000+ employees, 30+ countries) is looking for a Design Verification Team Lead to drive verification on complex mixed-signal ASICs. This is an ideal step-up role for someone who\u2019s led a small team (2-3 engineers) and wants more ownership, without moving into heavy people management. The package is [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[686,698],"consultants":[801],"industry":[],"class_list":["post-104135","jobs","type-jobs","status-publish","hentry","consultants-steph-hutchinson"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Design Verification Team Lead (Mixed-Signal ASIC) - Scotland<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/us\/jobs\/design-verification-team-lead-mixed-signal-asic-444642\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Design Verification Team Lead (Mixed-Signal ASIC) - Scotland\" \/>\n<meta property=\"og:description\" content=\"Apply to Design Verification Team Lead (Mixed-Signal ASIC) - Edinburgh, Scotland. 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