{"id":145970,"date":"2026-06-12T00:00:00","date_gmt":"2026-06-11T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/lead-physical-design-engineer-472759\/"},"modified":"2026-07-24T10:06:09","modified_gmt":"2026-07-24T09:06:09","slug":"lead-physical-design-engineer-472759","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/lead-physical-design-engineer-472759\/","title":{"rendered":"Lead Physical Design Engineer"},"content":{"rendered":"<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Our client is building a world-class silicon team and is looking for a Lead Physical Design Engineer to take ownership of the complete RTL-to-GDSII implementation flow for complex IP and SoC subsystems. This is a hands-on leadership role where you\u2019ll not only define methodologies and drive execution but also help scale a new backend team around you.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">In this position, you\u2019ll define best practices, own PPA and sign-off quality, and act as the bridge between digital design, custom design, and verification teams. The role combines deep technical involvement with the opportunity to shape the physical design strategy from the ground up.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Key responsibilities<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>End-to-end ownership:<\/strong> Oversee the entire RTL-to-GDSII flow \u2014 from synthesis and floorplanning through place &amp; route, CTS, STA, and sign-off<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Methodology &amp; flow:<\/strong> Define, maintain, and automate a robust implementation flow including constraints, UPF\/CPF, and sign-off checks<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>PPA &amp; closure:<\/strong> Drive timing and power closure across multiple corners and modes; lead ECO cycles and ensure strong correlation between synthesis, P&amp;R, and sign-off<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Integration:<\/strong> Handle integration of custom macros, SRAMs, and I\/O, including clocking strategy, CDC, and hierarchical designs<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Low-power design:<\/strong> Own power intent definition and implementation, including isolation, retention, and level-shifting strategies<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Team leadership:<\/strong> Build and mentor a backend team (5+ engineers), define ownership areas, and establish repeatable, high-quality sign-off standards<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Automation:<\/strong> Develop reproducible, automated flows using Tcl\/Python, CI\/CD pipelines, and metrics dashboards for continuous improvement<\/span><\/li>\n<li style=\"margin: 0cm 0cm 8pt 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Foundry interface:<\/strong> Collaborate closely with foundry partners on PDK updates, reliability rules, and design sign-off requirements<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Skills &amp; experience<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">5+ full tapeouts owning blocks or subsystems through to sign-off<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Deep expertise in one major EDA tool chain (Synopsys or Cadence)<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Proven experience in timing closure, MCMM STA, and hierarchical design integration<\/span><\/li>\n<li style=\"margin: 0cm 0cm 8pt 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Strong knowledge of UPF\/CPF for multi-voltage and power-gated designs<\/span><\/li>\n<\/ul>\n<ul style=\"margin-top: 0cm;margin-bottom: 0cm\" type=\"disc\">\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Hands-on experience with grid planning, IR\/EM analysis, power optimisation, and ECO implementation<\/span><\/li>\n<li style=\"margin-top: 0cm;margin-right: 0cm;margin-bottom: 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Confident in taking technical ownership and guiding others towards sign-off-quality results.<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">For more information, please contact Jordan Browne at IC Resources.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Our client is building a world-class silicon team and is looking for a Lead Physical Design Engineer to take ownership of the complete RTL-to-GDSII implementation flow for complex IP and SoC subsystems. This is a hands-on leadership role where you\u2019ll not only define methodologies and drive execution but also help scale a new backend team [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709,682],"job_skillset":[],"consultants":[239],"industry":[],"class_list":["post-145970","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Lead Physical Design Engineer - Switzerland<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/us\/jobs\/lead-physical-design-engineer-472759\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Lead Physical Design Engineer - Switzerland\" \/>\n<meta property=\"og:description\" content=\"Apply to Lead Physical Design Engineer - Zurich, Switzerland. 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