{"id":145992,"date":"2026-06-12T00:00:00","date_gmt":"2026-06-11T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/principal-staff-verification-engineer-472884\/"},"modified":"2026-08-15T22:07:36","modified_gmt":"2026-08-15T21:07:36","slug":"principal-staff-verification-engineer-472884","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/principal-staff-verification-engineer-472884\/","title":{"rendered":"Principal Staff Verification Engineer"},"content":{"rendered":"<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>A US-based start-up has recently expanded into the UK and is building a cutting-edge hardware team<\/strong> comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team, this company offers a unique opportunity to be part of the AI revolution from the ground up.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">As AI and computing rapidly evolve, there is an increasing demand for sophisticated platforms that integrate a wide range of processors\u2014including CPUs, GPUs, and neural accelerators and this is where you come in!<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">You will be joining a Fabric IP company as a Design Verification Engineer, contributing your strong background in developing testbenches and writing test sequences for complex IPs. In this role, you will play a pivotal part in shaping the company\u2019s technology portfolio\u2014bringing both technical expertise and creative problem-solving to innovative hardware solutions.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Responsibilities:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Write UVM\/SystemVerilog code to implement the test plan, checkers, and scoreboards<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Collaborate with software teams to define and implement configurable testbenches<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Work with design teams test plans, failure debug, coverage, etc<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Qualifications and preferred skills<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">BS, MS in&nbsp;Electrical Engineering, Computer&nbsp;Engineering&nbsp;or&nbsp;Computer&nbsp;Science<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">6+ years and current hands-on experience in block-level\/IP-level\/SoC-level verification<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficiency in Verilog, SystemVerilog<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with industry-standard EDA tools for simulation and debug<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Deep experience with UVM-based testbenches<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience with modern programming languages like Python<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Knowledge of Arm AMBA protocols such as AXI, APB, and AHB<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Understanding of Arm CHI protocol is a plus<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience on working with IP&#8217;s for caches, cache coherency, memory subsystems, interconnects, and NoC&#8217;s is a plus<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience with formal verification techniques, emulation platforms is a plus<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Excellent problem-solving skills and attention to detail<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong communication and collaboration skills<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">On offer is a competitive base salary of up to \u00a3120,000 (dependent on experience), along with share options and a performance-based bonus scheme<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">This is a rare opportunity to join the company as one of the first engineers in the UK\u2014and among a select few globally\u2014helping to shape and build a world-class hardware team from the ground up<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>To be considered for this role, you must already be living and working in the United Kingdom and happy to work onsite in either Bristol or Cambridge.<\/strong><\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">For more information, please contact Rachel Mason.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>A US-based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team, this company offers a unique opportunity to be part of the AI revolution from the ground up. As AI and computing rapidly evolve, there is [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[698],"consultants":[408],"industry":[],"class_list":["post-145992","jobs","type-jobs","status-publish","hentry","consultants-rachel-mason"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Principal Staff Verification Engineer - England<\/title>\n<meta name=\"description\" content=\"Apply to Principal Staff Verification Engineer - Cambridgeshire, England. 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