{"id":194050,"date":"2026-08-10T00:00:00","date_gmt":"2026-08-09T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-verification-engineer-498533\/"},"modified":"2026-08-11T10:04:38","modified_gmt":"2026-08-11T09:04:38","slug":"senior-verification-engineer-498533","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/senior-verification-engineer-498533\/","title":{"rendered":"Senior Verification Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">Join a world-class semiconductor powerhouse in Edinburgh, one of Europe\u2019s most attractive tech hubs. Known for its thriving semiconductor ecosystem, outstanding quality of life, and easy access to nature, Edinburgh offers the perfect balance between cutting-edge engineering work and lifestyle. This role provides an opportunity for experienced verification engineers to make a long-term move to the UK.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"> In this role, you\u2019ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Key responsibilities<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Create and maintain UVM-based SystemVerilog testbenches<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Write, debug, and execute test cases to verify functionality, performance, and corner cases<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Perform block-level and full-chip verification, including simulation, coverage analysis, and regression management<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Collaborate closely with design engineers to interpret specifications and define verification requirements<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Analyse and resolve issues discovered during verification and post-silicon validation<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Mentor junior engineers and drive improvements in verification methodologies and infrastructure<\/span><\/li>\n<li style=\"margin: 0cm 0cm 8pt 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Participate in code reviews and contribute to continuous improvement of design and verification best practices<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Qualifications<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">5+ years\u2019 experience in digital and\/or mixed-signal design verification<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Strong proficiency in<strong> <\/strong>SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Solid understanding of digital design principles, RTL design, and ASIC development flows<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Experience with scripting languages (Python, Perl, Shell, etc.)<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques<\/span><\/li>\n<li style=\"margin: 0cm 0cm 8pt 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Excellent problem-solving skills and attention to detail<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>What\u2019s on offer<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Competitive base salary plus RSUs and annual bonus<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">A collaborative, innovative working environment<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Fore more information on this role or others then please contact Jordan Browne for more information. <\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Join a world-class semiconductor powerhouse in Edinburgh, one of Europe\u2019s most attractive tech hubs. Known for its thriving semiconductor ecosystem, outstanding quality of life, and easy access to nature, Edinburgh offers the perfect balance between cutting-edge engineering work and lifestyle. This role provides an opportunity for experienced verification engineers to make a long-term move to [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[698],"consultants":[239],"industry":[],"class_list":["post-194050","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior Verification Engineer - Scotland<\/title>\n<meta name=\"description\" content=\"Apply to Senior Verification Engineer - Edinburgh, Scotland. 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