{"id":220302,"date":"2026-09-15T00:00:00","date_gmt":"2026-09-14T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/serdes-ic-architect-514323\/"},"modified":"2026-10-07T22:07:44","modified_gmt":"2026-10-07T21:07:44","slug":"serdes-ic-architect-514323","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/serdes-ic-architect-514323\/","title":{"rendered":"SerDes IC Architect"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">I am recruiting for a SerDes Architecture and Modelling Engineer to join my client\u2019s team in Lausanne, Switzerland. This is a research and architecture-focused position for an engineer who enjoys investigating new ideas, developing algorithms and creating models to explore the performance of next-generation high-speed communication systems.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The role has a strong emphasis on research, innovation and developing new architectural concepts rather than simply implementing established designs.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">As a SerDes Architecture and Modelling Engineer, you will:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Research and develop new concepts for high-speed serial communication systems<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Build system level models to investigate, compare and optimise new architectures<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Develop signal processing algorithms and evaluate their impact on link performance<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Use MATLAB, Python or C++ to model communication systems and test new ideas<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Work with architects and IC designers to translate research concepts into practical transceiver architectures<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Analyse system limitations including signal integrity, noise, power and clock recovery<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Define link budgets and block-level specifications based on system requirements<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Support analog, digital and verification teams throughout the development process<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">My client is looking for an engineer with a strong research background in signal processing, communications, control theory or mathematical modelling.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Relevant experience could include:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Research and development of new communication or signal processing techniques<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong understanding of digital algorithms and control theory<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience developing and implementing signal processing algorithms<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">System-level modelling of digital communication systems<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong programming skills in MATLAB, Python or C++<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Understanding of SerDes, clock recovery or other high-speed communication systems<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Knowledge of signal integrity and analog circuit behaviour<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience with SPICE or Spectre would be useful<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The role is aimed at someone with 5+ years of experience in semiconductor, telecommunications, communications research or scientific software development.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">A Bachelor&#8217;s degree or higher in Electrical Engineering, Electronic Engineering, Communications, Computer Science or a related field is expected.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The SerDes Architecture and Modelling Engineer position would suit someone who enjoys working in an R&amp;D environment, challenging existing approaches and turning research ideas into new system architectures.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The role requires a minimum of 3 days on site in Lausanne.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Get in touch with Parm Shergill for more information.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>I am recruiting for a SerDes Architecture and Modelling Engineer to join my client\u2019s team in Lausanne, Switzerland. This is a research and architecture-focused position for an engineer who enjoys investigating new ideas, developing algorithms and creating models to explore the performance of next-generation high-speed communication systems. The role has a strong emphasis on research, [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[686,687],"consultants":[21],"industry":[],"class_list":["post-220302","jobs","type-jobs","status-publish","hentry","consultants-parm-shergill"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.6 (Yoast SEO v28.6) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>SerDes IC Architect - Switzerland<\/title>\n<meta name=\"description\" content=\"Apply to SerDes IC Architect - Lausanne, Switzerland. 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