{"id":225161,"date":"2026-09-21T00:00:00","date_gmt":"2026-09-20T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/principal-hardware-architect-518611\/"},"modified":"2026-09-27T06:06:41","modified_gmt":"2026-09-27T05:06:41","slug":"principal-hardware-architect-518611","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/principal-hardware-architect-518611\/","title":{"rendered":"Principal Hardware Architect"},"content":{"rendered":"

Principal SoC \/ NoC Architect \u2013 Cache Coherency<\/span><\/h1>\n

France | \u20ac65,000\u2013\u20ac100,000 | SoC \/ NoC \/ Chiplets \/ CHI \/ UCIe<\/span><\/p>\n

Want to work on the architecture behind some of the world\u2019s most advanced SoCs and chiplet-based systems?<\/span><\/p>\n

I\u2019m working with a global semiconductor IP company whose technology is used by leading chip companies to build high-performance, power-efficient SoCs.<\/span><\/p>\n

They are now looking for a Principal Hardware Architect \/ Cache Coherency Architect to help define and evolve next-generation cache-coherent Network-on-Chip IP.<\/span><\/p>\n

What you\u2019ll work on<\/span><\/h2>\n
    \n
  • Define cache coherency architectures for complex SoCs<\/span><\/li>\n
  • Develop scalable coherent interconnect solutions for multi-core and chiplet systems<\/span><\/li>\n
  • Work on NoC architecture and microarchitecture<\/span><\/li>\n
  • Optimise latency, bandwidth, power and area<\/span><\/li>\n
  • Define PPA targets for configurable IP<\/span><\/li>\n
  • Work with technologies including CHI, UCIe, PCIe and UA Link<\/span><\/li>\n
  • Support verification and emulation teams on coherency behaviour<\/span><\/li>\n
  • Work across hardware, software, product and customer-facing teams<\/span><\/li>\n
  • Influence future interconnect and chiplet architecture<\/span><\/li>\n<\/ul>\n

    What we\u2019re looking for<\/span><\/h2>\n

    Strong experience in:<\/span><\/p>\n

    Cache Coherency | SoC Architecture | NoC Architecture | Memory Hierarchies | CHI | UCIe | PCIe | Chiplets | Interconnect | RTL<\/span><\/p>\n

    You may currently be working as a:<\/span><\/p>\n

    SoC Architect, NoC Architect, Cache Coherency Architect, Principal Hardware Architect or senior ASIC Design Engineer moving into architecture.<\/span><\/p>\n

    Why this one stands out<\/span><\/h2>\n

    This company operates right at the centre of one of the biggest challenges in modern semiconductor design: how increasingly complex processors, accelerators, memory systems and chiplets communicate efficiently.<\/span><\/p>\n

    You\u2019ll work on commercially deployed IP used in advanced semiconductor products, while solving genuinely difficult problems in coherency, interconnect and system architecture.<\/span><\/p>\n

    Salary: \u20ac65,000\u2013\u20ac100,000 base<\/span>
    Location: France<\/span>
    Eligibility: Existing EU work rights preferred<\/span><\/p>\n

    If you\u2019re working in cache coherency, NoC, SoC architecture or chiplet interconnect, I\u2019d be keen to speak with you contact Steph Hutchinson for more details.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

    Principal SoC \/ NoC Architect \u2013 Cache Coherency France | \u20ac65,000\u2013\u20ac100,000 | SoC \/ NoC \/ Chiplets \/ CHI \/ UCIe Want to work on the architecture behind some of the world\u2019s most advanced SoCs and chiplet-based systems? I\u2019m working with a global semiconductor IP company whose technology is used by leading chip companies to […]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[801],"industry":[],"class_list":["post-225161","jobs","type-jobs","status-publish","hentry","consultants-steph-hutchinson"],"acf":[],"yoast_head":"\nPrincipal Hardware Architect - France<\/title>\n<meta name=\"description\" content=\"Apply to Principal Hardware Architect - Ile de France, France. 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