{"id":225166,"date":"2026-09-17T00:00:00","date_gmt":"2026-09-16T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-verification-engineer-516621\/"},"modified":"2026-09-30T10:10:10","modified_gmt":"2026-09-30T09:10:10","slug":"senior-verification-engineer-516621","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/senior-verification-engineer-516621\/","title":{"rendered":"Senior Verification Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">This is a unique opportunity to join an innovative quantum technology company as one of the first UVM Verification Engineers within its growing Oxford team.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">You will have significant autonomy and the opportunity to take ownership of the verification environment, helping to define the methodology, infrastructure and best practices used across the team.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The company is developing advanced quantum computing systems, and the role offers an unusual combination of working within a fast-paced, start-up-style environment while benefiting from the backing and resources of a global organisation.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">You will work at the intersection of FPGA development and quantum technology, helping to develop and verify the sophisticated control systems that underpin next-generation quantum computing platforms.<\/span><\/p>\n<p><strong><span style=\"font-family: Verdana;font-size: 14px\">The Role<\/span><\/strong><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">As a Senior Verification Engineer, you will play a key role in developing the verification environments and methodologies used across complex FPGA designs.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Working closely with FPGA and RTL Design Engineers, you will take ownership of verification infrastructure and help establish best practices across simulation, verification and test.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Key responsibilities will include:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Architecting, developing and maintaining advanced UVM\/SystemVerilog verification environments for complex FPGA designs<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Defining and executing comprehensive verification plans<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Developing constrained-random test environments and driving functional and code coverage closure<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Working closely with RTL Design Engineers to debug failures, identify root causes and improve overall design quality<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Developing and maintaining automated regression environments<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Supporting continuous integration and verification workflows throughout the FPGA development lifecycle<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Helping define and drive verification methodology and best practices across the wider FPGA team<\/span><\/li>\n<\/ul>\n<p><strong><span style=\"font-family: Verdana;font-size: 14px\">Requirements<\/span><\/strong><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">This role would suit an engineer with approximately 4\u20137 years of professional experience within an FPGA or ASIC verification environment and a strong background in modern verification methodologies.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Key experience includes:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong SystemVerilog and UVM experience<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience architecting and developing verification environments<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Constrained-random and coverage-driven verification experience<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Verification planning and requirements gathering<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Python for scripting and test automation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong debugging and problem-solving skills<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience working closely with RTL and\/or FPGA design teams<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">This would particularly suit a Verification Engineer who wants to move into a position with greater ownership and autonomy, helping to shape verification architecture and methodology rather than simply working within an established environment.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">It also offers the opportunity to apply your verification experience to complex FPGA designs within the rapidly developing field of quantum technology.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">On offer is a competitive base salary, RSUs and bonus.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Visa sponsorship and relocation support can be provided for engineers who are already living and working in the UK and require support to move to Oxford.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Unfortunately, relocation and visa sponsorship for candidates currently based outside the UK are not available at this time.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">For more details please contact Rachel Mason.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This is a unique opportunity to join an innovative quantum technology company as one of the first UVM Verification Engineers within its growing Oxford team. You will have significant autonomy and the opportunity to take ownership of the verification environment, helping to define the methodology, infrastructure and best practices used across the team. The company [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[698],"consultants":[408],"industry":[],"class_list":["post-225166","jobs","type-jobs","status-publish","hentry","consultants-rachel-mason"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v28.5) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior Verification Engineer - England<\/title>\n<meta name=\"description\" content=\"Apply to Senior Verification Engineer - Oxfordshire, England. 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