This is an exciting opportunity for Digital ASIC Design Engineer to join an established semiconductor engineering team working on the next generation of low power wireless SoCs.<\/p>\n
The ASIC RTL Design Engineer will be involved across the front end development flow, from architecture and RTL development through integration, verification and ultimately silicon. The role offers strong technical ownership and the chance to work on complex digital designs that are used in high volume connected products.<\/p>\n
The role will involve:<\/p>\n
\u2022 Developing RTL for complex digital ICs and SoC designs
\u2022 Working across architecture, design and integration of IP and larger subsystems
\u2022 Supporting the development of designs through to tape out and silicon
\u2022 Working closely with verification, DFT, software and physical implementation teams
\u2022 Contributing to synthesis, timing and design quality activities
\u2022 Working on low power design methodologies and optimising designs for performance and efficiency
\u2022 Using scripting and automation to improve design and development flows
\u2022 Supporting technical discussions and sharing knowledge across the wider engineering team<\/p>\n
The ideal ASIC RTL Design Engineer will have:<\/p>\n
\u2022 Experience in ASIC, SoC or digital IC design
\u2022 Solid hands on experience with Verilog or SystemVerilog RTL
\u2022 Good understanding of the digital design flow from RTL through synthesis and implementation
\u2022 Experience with low power design is desirable but not essential <\/p>\n
This Digital ASIC Design Engineer position would suit an engineer who enjoys being technically involved throughout the development cycle and wants to take ownership of complex digital designs from concept through to silicon.<\/p>\n
For more information, please contact Jordan Browne.<\/p>\n","protected":false},"excerpt":{"rendered":"
This is an exciting opportunity for Digital ASIC Design Engineer to join an established semiconductor engineering team working on the next generation of low power wireless SoCs. The ASIC RTL Design Engineer will be involved across the front end development flow, from architecture and RTL development through integration, verification and ultimately silicon. The role offers […]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[239],"industry":[],"class_list":["post-246542","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"\n