{"id":31049,"date":"2026-01-06T00:00:00","date_gmt":"2026-01-06T00:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/design-verification-engineer-388903\/"},"modified":"2026-07-25T10:08:39","modified_gmt":"2026-07-25T09:08:39","slug":"design-verification-engineer-388903","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/design-verification-engineer-388903\/","title":{"rendered":"Design Verification Engineer"},"content":{"rendered":"<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">An excellent opportunity has arisen to join a global leader in advanced semiconductor technologies. This role offers the chance to work on cutting-edge 5nm designs, supporting the latest PCIe interfaces, protocols, and NAND flash solutions.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">While part of a large international organisation, the UK site operates with the feel of a fast-moving startup but with the stability and backing of a major company. The team builds on over a decade of SSD design expertise, applying a proven methodology that combines RTL design with high-speed microcode engines\u2014delivering flexibility to meet new requirements while minimising the risk of re-spins.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">The ASIC team is involved in every stage of the development flow\u2014from requirements capture and architecture through to development, verification, tape-out, and post-silicon support. This provides excellent opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise in areas such as UVM-based verification.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance accelerators, and multi-CPU architectures. Team responsibilities span SoC architecture, RTL design, verification, synthesis, FPGA prototyping, and validation.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Why Oxfordshire?<\/strong><\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Oxfordshire offers a fantastic quality of life, combining a world-renowned university city with beautiful countryside. With excellent schools, cultural attractions, and easy access to London and Heathrow, it\u2019s an ideal location for both professionals and families.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Essential qualifications and skills<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Bachelor\u2019s or Master\u2019s degree in Electronic Engineering (or related field)<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Experience in digital ASIC design and verification, including:<\/span>\n<ul style=\"list-style-type: circle;margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Defining functional requirements for verification environments &amp; metrics<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">SystemVerilog UVM testbenches<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Formal proof verification<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Understanding of C test cases and C code<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Scripting languages (e.g. Python, Perl, TCL)<\/span><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Desirable skills<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Experience with formal verification tools (JasperGold, VC Formal)<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with C\/C++ development<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Prior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred)<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 0cm 36pt;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>What\u2019s on offer<\/strong><\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Competitive base salary<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Hybrid working model<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Generous company pension scheme<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Private health insurance<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Visa sponsorship and relocation support for experienced engineers<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\">&nbsp;<\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">For more information or a confidential discussion, please contact Rachel Mason at IC Resources.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>An excellent opportunity has arisen to join a global leader in advanced semiconductor technologies. This role offers the chance to work on cutting-edge 5nm designs, supporting the latest PCIe interfaces, protocols, and NAND flash solutions. &nbsp; While part of a large international organisation, the UK site operates with the feel of a fast-moving startup but [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[698],"consultants":[239],"industry":[],"class_list":["post-31049","jobs","type-jobs","status-publish","hentry","consultants-jordan-browne"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Design Verification Engineer - England<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/us\/jobs\/design-verification-engineer-388903\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Design Verification Engineer - England\" \/>\n<meta property=\"og:description\" content=\"Apply to Design Verification Engineer - Oxfordshire, England. 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