{"id":72150,"date":"2026-03-02T00:00:00","date_gmt":"2026-03-02T00:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/analog-ic-layout-engineer-421100\/"},"modified":"2026-08-16T02:10:05","modified_gmt":"2026-08-16T01:10:05","slug":"analog-ic-layout-engineer-421100","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/us\/jobs\/analog-ic-layout-engineer-421100\/","title":{"rendered":"Analog IC Layout Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">I am seeking an Analog Mixed Signal IC Layout Engineer to join my client\u2019s European design centre in Prague. The team designs IP on advanced CMOS nodes, including FinFET and GAA, for data centre, automotive, AI and low power IoT applications.<\/span><\/p>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">Responsibilities<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Create full custom layout for analog and mixed signal blocks on advanced CMOS processes<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Collaborate with circuit designers on floorplans and device placement to meet matching and performance targets<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Perform extraction and assist with post layout simulation to verify behaviour against schematic<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Run DRC, LVS and ERC and work to close physical verification issues<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Diagnose layout related silicon issues during bring up and support lab debug and validation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Improve layout methodology and produce clear documentation for reuse<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">Key skills<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong background in analog and mixed signal layout techniques, including matching, shielding and guard rings<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Familiar with layout considerations for:<\/span>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Bandgap references and precision amplifiers<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Precision sense amplifiers<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">I\/O and interface circuits<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Low jitter PLLs and clocking blocks<\/span><\/li>\n<\/ul>\n<\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficient with industry-standard layout and verification tool flows<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">This role is open only to candidates who already have the right to work without requiring sponsorship.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">If you are local or willing to relocate and would like to work on cutting edge semiconductor technology, get in touch with Parm Shergill.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>I am seeking an Analog Mixed Signal IC Layout Engineer to join my client\u2019s European design centre in Prague. The team designs IP on advanced CMOS nodes, including FinFET and GAA, for data centre, automotive, AI and low power IoT applications. Responsibilities Create full custom layout for analog and mixed signal blocks on advanced CMOS [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[],"consultants":[21],"industry":[],"class_list":["post-72150","jobs","type-jobs","status-publish","hentry","consultants-parm-shergill"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Analog IC Layout Engineer - Czechia<\/title>\n<meta name=\"description\" content=\"Apply to Analog IC Layout Engineer - , Czechia. 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