Senior Design Verification Engineer

Senior Digital Verification Engineer

London

This is an opportunity to take a technically influential role within a growing semiconductor business, working on complex mixed-signal ASIC technology for a highly innovative medical application.

I am working with an innovative, early-stage technology company operating at the intersection of neurotechnology and semiconductor engineering. They are developing advanced IC solutions for implantable medical devices, designed to support the management and treatment of neurological conditions.

This is an opportunity to join a pioneering engineering team working on next-generation ASIC technology with the potential to make a meaningful difference in healthcare.

The Role

As a Senior Digital Verification Engineer, you will take ownership of the verification strategy and execution for the digital subsystems within next-generation mixed-signal ASICs.

I am looking for an experienced verification engineer who enjoys building robust, scalable verification environments and takes pride in identifying issues before they reach silicon.

You will be the first Verification expert into the team and so you will define and lead verification activities from block level through to full-chip and mixed-signal system verification, driving verification closure through to tape-out and silicon bring-up.

Key Responsibilities

• Verification Strategy: Own and define the digital verification strategy for mixed-signal ASICs, from block level through to full-chip sign-off. Develop verification plans, establish coverage targets and drive verification closure through to tape-out.
• Testbench Development: Build reusable, self-checking SystemVerilog testbenches using UVM or equivalent methodologies. Develop constrained-random stimulus, assertions, scoreboards and reference models.
• Verification Execution: Manage simulation regressions, debug RTL issues, analyse coverage and develop automation infrastructure using scripting languages such as Python, Tcl or Shell.
• Mixed-Signal and Safety Verification: Work closely with analogue design teams to verify mixed-signal interfaces, clocking, power sequencing and calibration. Validate safety mechanisms through fault injection and support risk-management activities.
• Silicon Bring-up: Support post-silicon bring-up, laboratory testing and validation, correlating hardware results with pre-silicon verification.
• Technical Leadership: Collaborate across multidisciplinary engineering teams, lead verification reviews, mentor engineers and help shape verification methodologies and processes as the team grows.

Essential Requirements

• 7+ years‘ experience in digital ASIC verification.
• Proven experience taking digital ASIC blocks or subsystems through verification and tape-out sign-off.
• Strong SystemVerilog verification experience, including structured self-checking testbenches (UVM or equivalent), constrained-random stimulus, assertions (SVA) and functional coverage.
• Experience developing verification plans and driving coverage closure.
• Strong debugging skills and the ability to understand and analyse RTL written in Verilog/SystemVerilog.
• Scripting experience using Python, Tcl, Shell or similar languages for regression automation and results analysis.
• Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced R&D environment.

This is an opportunity to take a technically influential role within a growing semiconductor business, working on complex mixed-signal ASIC technology for a highly innovative medical application.

You will have significant ownership of the verification strategy, the opportunity to influence engineering processes and the chance to contribute to technology that could have a meaningful impact on patients‘ lives.

Visa sponsorship can be provided but you must currently be residing in the United Kingdom.

For more information, please contact Rachel Mason at IC Resources