Senior IC Layout Engineer – London

This is a new opportunity for a Senior IC Layout Engineer to join a rapidly expanding deep-tech start-up company based in North London. Flexible working is available, ideally a minimum of 2 days a week in the office.

This is a chance to work on something truly remarkable. Our client has developed the world’s first CMOS silicon chip for quantum computing – their work will have an enormous impact on so many application areas. They now seek a Senior IC Layout Engineer to focus on the layout of analog and mixed-signal IP, capable of operating at cryogenic temperatures as well the layout and characterisation of qubits based on commercial CMOS processes. 

The role will involve:

• Hands-on block-level layout design and verification
• Parasitic extraction and optimisation of layouts in close collaboration with the design team
• Top -level floor-planning, routing and signoff
• Providing tool/flow support for analogue and layout design teams

We’re looking for an experienced Analog IC Layout Engineer with:

• Solid skills working within a Cadence environment
• Skills in Cadence Virtuoso Layout Suite (X)L including PCell Designer

• Expertise in DRC, LVS, & Parasitic Extraction with Mentor Calibre or Cadence PVS/QRC
• Demonstrated experience in deep sub-micron processes
• Superb communication skills, with the passion and drive to contribute to an fast-moving start-up

A competitive basic salary is on offer together with benefits including company share package. 

To learn more or to apply, please contact Caroline Pye @ IC Resources today.