SoC Top RTL Lead Engineer

SoC Top RTL Lead Engineer

We are seeking an experienced and highly skilled SoC Top RTL Lead Engineer to take ownership of the top-level RTL design for our high-performance System-on-Chips (SoCs). This is a hands-on technical leadership role where you will lead the integration of subsystems into the SoC top, define critical architectures such as clock, reset, power, and IO, and drive the design process from specification to tape-out.

As the SoC Top RTL Lead Engineer, you will play a pivotal role in guiding a team of engineers, ensuring design excellence, and acting as the primary point of contact for top-level design across architecture, verification, and physical design teams.

Responsibilities

• SoC Top-Level Ownership: Lead the integration of CPU clusters, subsystems, and third-party IP into the SoC top-level RTL
• Team Leadership: Mentor and guide a team of RTL engineers, plan and prioritize their work, and establish design standards and best practices
• Reset Architecture: Define and implement the SoC reset architecture, including reset domains, sequencing, and synchronization
• Clock Architecture: Design and implement the SoC clock architecture, including clock topologies, generation, and distribution
• Power Infrastructure: Develop the power infrastructure for multiple power domains, including isolation strategies and power-on sequencing
• Signal Distribution: Plan and manage signal distribution across the SoC, addressing delay propagation and signal integrity
• External Interfaces: Define and manage the chip’s interfaces with external components, including pads, IOs, and low-level technology cells such as tri-state buffers, with a focus on ESD protection
• Design Closure: Own lint, CDC, and RDC closure at the SoC top level and drive the definition of UPF power intent
• Cross-Team Collaboration: Act as the technical interface with architecture, verification, DFT, and physical design teams, ensuring the SoC progresses smoothly to tape-out

Qualifications

• A degree in Electrical Engineering, Electronic Engineering, Computer Engineering, or a related field
• 8+ years of experience in digital/SoC design
• Strong hands-on RTL design experience using SystemVerilog/Verilog
• Proven experience leading SoC top-level RTL integration for large, high-performance SoCs
• A successful track record of contributing to one or more tape-outs of high-performance SoCs
• Expertise in SoC clock and reset architecture
• Experience with signal distribution, including delay propagation and signal integrity
• Hands-on experience managing interfaces with external components, including low-level technology cells such as pads and tri-state buffers
• Solid understanding of ESD protection concepts
• Demonstrated experience as a technical lead, mentoring engineers and coordinating work across teams
• Fluent in English, both written and spoken

Benefits

• Opportunity to work at one of Europe’s most promising deep-tech semiconductor scale-ups
• Accelerated career development with exposure to cutting-edge technologies such as confidential computing, memory isolation, and software security
• Flexible work arrangement: 4 days per week in the Barcelona office (city center) and 1 day working from home
• One week of work-from-anywhere in the world
• Competitive compensation package
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking

If you are passionate about leading the design of high-performance SoCs and thrive in a dynamic, innovative environment, we encourage you to apply for this exciting opportunity.

If you have a preexisting work permit for Spain (permanent residence in Spain or any EU passport) and think you have the right skills for this role, please contact Ane @ IC Resources with your CV and a time for a call!