SoC Top RTL INtegration Engineer

SoC Top RTL Integration Engineer

We are seeking a highly skilled and experienced SoC Top RTL Integration Engineer to join our team. In this senior, hands-on role, you will play a critical part in integrating multiple subsystems into the top level of high-performance System-on-Chips (SoCs). This position is ideal for an engineer with a proven track record of integrating large SoCs and successfully taking them to silicon.

Responsibilities:

As an SoC Top RTL Integration Engineer, your key responsibilities will include:

• Subsystem Integration: Integrate multiple subsystems, including CPU clusters, memory, accelerators, peripherals, and third-party IP, into the SoC top-level RTL
• Interconnects and Protocols: Connect subsystems through interconnects and NoCs using protocols such as AXI, APB, and CHI
• Chip IOs: Define and integrate the chip’s IOs, including connections to pads
• Timing Constraints: Write and maintain SDC timing constraints for the integrated design, collaborating closely with physical design teams
• Verification Checks: Run, debug, and close lint, CDC, and RDC checks at the SoC top level
• Clock, Reset, and Power Integration: Integrate the top-level clock, reset, and power infrastructure, contributing to UPF power intent
• Automation and Testing: Develop Python and C scripts and tests to automate integration flows and support bring-up
• Cross-Functional Collaboration: Work closely with architecture, verification, DFT, and physical design teams to drive the SoC through to tape-out

Qualifications:

• Degree in Electrical Engineering, Electronic Engineering, Computer Engineering, or a related field
• 8+ years of experience in digital/SoC design
• Strong hands-on RTL design experience (SystemVerilog/Verilog)
• Proven experience integrating multiple subsystems on large SoCs
• Experience connecting subsystems through interconnects and/or NoCs, with solid knowledge of AXI and APB
• Proven track record on one or more tape-outs
• Hands-on experience with lint, CDC, and RDC checks
• Experience writing and managing SDC constraints and integrating chip IOs
• Working knowledge of Python and C for scripting and automation (user level)

Nice to have:

• Knowledge of clock, reset, and power architectures
• Experience with the CHI coherent interconnect protocol
• Experience with UPF-based low-power design flows and pad ring integration

This is an exciting opportunity to work on cutting-edge SoC designs and contribute to the development of high-performance systems. You will collaborate with a talented and multidisciplinary team, driving innovation and excellence in the semiconductor industry. If you are passionate about SoC integration and have the expertise to deliver world-class designs, we encourage you to apply.

For more information and to apply, please contact Ane@ IC Resources with your CV and a time for a call!