ASIC Design Engineer

Want to work on the interconnect technology sitting at the heart of some of the world’s most advanced SoCs?

I’m working with a global semiconductor IP company whose technology is used across AI, automotive, consumer electronics, data centres, satellites and advanced computing.

They are now hiring a Staff Hardware Design Engineer to work on highly configurable Network-on-Chip (NoC) IP and complex SoC architectures.

What you’ll work on

• Define architecture specifications for complex NoC / SoC IP
• Design and develop RTL hardware blocks
• Work across the full ASIC design flow
• Contribute to verification, synthesis, timing, power and DFT
• Work closely with hardware, software and application engineering teams
• Support existing IP and help solve complex technical issues
• Influence the evolution of highly configurable interconnect products

What they’re looking for

You’ll ideally have 5+ years of ASIC / SoC / IP design experience, with strong knowledge of:

RTL Design | SystemVerilog | Verilog | VHDL | SoC Design | NoC | ASIC Design | Synthesis | STA | DFT | Timing Closure | Power Closure

Experience with some of the following would be particularly relevant:

AMBA | AXI | PCIe | CXL | OCP | ARM | RISC-V | SystemC | C++ | Python | Cadence | Synopsys | Siemens EDA

Why consider it?

This is a strong opportunity for an experienced RTL / SoC designer who wants to move beyond isolated block design and work closer to system-level architecture and advanced interconnect IP.

You’ll be working on technology designed to solve one of the biggest challenges in modern semiconductor development: efficiently connecting increasingly complex processors, accelerators, memory and IP inside large SoCs.

Salary: €65,000–€75,000 gross base
Location: Montigny-le-Bretonneux, France
Eligibility: Candidates should already have the right to work in France / the EU

If your background is in ASIC Design, RTL, SoC IP or Network-on-Chip, I’d be keen to speak with you please contact Steph Hutchinson for more details.