Design Verification Engineer

Location: Sofia, Bulgaria | Hybrid | ASIC | SystemVerilog | UVM | PCIe

Looking for your next challenge in semiconductor design verification?

I’m working with a leading global semiconductor company that’s looking for a Design Verification Engineer to join its growing team in Sofia, Bulgaria. You’ll work on cutting-edge PCIe and CXL controller IP, helping deliver next-generation connectivity solutions used across AI, data centre and high-performance computing applications.

What you’ll be doing:

• RTL integration using Verilog
• ASIC/IP verification using SystemVerilog and UVM/Avery
• Develop and maintain verification environments and testbenches
• Support IP integration and customer projects
• Drive improvements to verification methodologies and processes
• Collaborate with engineering teams across Europe, the US and Asia

What you’ll bring:

• Experience in ASIC/VLSI Design Verification
• Strong SystemVerilog and Verilog skills
• Experience with UVM or Avery VIP
• Python and/or Shell scripting experience
• Excellent debugging and problem-solving skills
• PCIe experience is a bonus
• Fluent English

What’s on offer:

• Competitive salary + bonus
• Hybrid working in Sofia or fully remote elsewhere in Bulgaria
• 25 days annual leave
• Private healthcare
• Food vouchers
• Multisport card
• Free office lunches twice a week
• The opportunity to work on world-class semiconductor technology

Interested? Apply with your CV in English or get in touch for a confidential chat.