Digital Verification Engineer

An exciting opportunity has arisen for a Verification Engineer to join an innovative technology company developing next-generation computing solutions.

Working within a highly experienced engineering team, you will contribute to the verification of complex digital designs, helping to deliver cutting-edge products from concept through to silicon.

The role will involve:

• Developing and maintaining SystemVerilog/UVM verification environments
• Creating test plans, testbenches and verification IP
• Executing simulation and regression testing and analysing results
• Working closely with design engineers to debug and resolve issues
• Contributing to coverage closure and verification sign-off activities

The ideal candidate will have:

• Experience in digital IC or SoC verification
• Strong knowledge of SystemVerilog and UVM methodologies
• Understanding of constrained-random and coverage-driven verification techniques
• Good debugging and problem-solving skills.
• A collaborative approach and the desire to work as part of a highly technical engineering team

This is an opportunity to join a well-funded, ambitious organisation tackling complex engineering challenges in a fast-paced and innovative environment. The company offers the chance to work on industry-leading technology alongside some of the brightest engineers in the sector.

For more information, please contact Jordan Browne.