Lead DFT Engineer

I’m currently working with a heavily funded, cutting-edge semiconductor company developing next-generation AI hardware designed to overcome one of the biggest challenges facing modern computing.

As AI models continue to grow exponentially in complexity, today’s silicon is reaching its limits. This team is designing a completely new class of high-performance processors that will enable the next wave of AI acceleration.

They’re now looking for a Lead DFT Engineer to take ownership of the Design-for-Test architecture for a large, complex AI SoC.

This is a genuine technical leadership position where you’ll define the DFT methodology and architecture from the ground up while remaining close to implementation throughout the full silicon lifecycle.

You’ll work alongside architecture, RTL, verification, physical implementation and silicon teams to ensure robust testability from concept through to production.

Responsibilities

• Own the DFT architecture for a large, high-performance AI SoC
• Define DFT strategy, methodology, flows and sign-off criteria
• Architect scan insertion, scan compression and ATPG solutions
• Define hierarchical DFT implementation across large multi-core designs
• Develop MBIST, LBIST and boundary scan strategies
• Define memory test and repair methodologies for large embedded SRAMs
• Establish power-aware and at-speed manufacturing test approaches
• Work closely with RTL and Physical Design teams to ensure clean DFT integration
• Support silicon bring-up, production test, ATPG debug and yield optimisation
• Provide technical leadership and mentor other DFT engineers

What they’re looking for

• Around 10+ years’ experience in ASIC/SoC Design-for-Test
• Proven ownership of DFT architecture on at least one complex tape-out
• Strong expertise in:
  • Scan architecture
  • Scan compression
  • ATPG
  • MBIST
  • LBIST
  • Boundary Scan (JTAG)
• Experience using Synopsys DFT/TestMAX or Siemens Tessent tool suites
• Strong understanding of clocking, resets, power domains and physical implementation constraints
• Experience supporting silicon bring-up, manufacturing test and yield improvement

This opportunity would suit someone who enjoys solving difficult technical problems, defining methodology rather than simply following it, and taking ownership of complex engineering challenges. You’ll be comfortable balancing architectural thinking with hands-on implementation and will enjoy working in a collaborative, fast-paced engineering environment where your technical decisions have a direct impact on the product.

If you’re interested in learning more, I’d be happy to share further details confidentially. 

Contact Rachel at IC Resources