Principal Physical Implementation Engineer

North Brabant, Netherlands
Fantastic salary and other benefits
Job ID: 527198
Jordan Browne
Jordan Browne

ASIC | Verification | Physical Design

+44 (0)118 907 3075

jordan.browne@ic-resources.com

An ambitious semiconductor business developing advanced silicon for next-generation AI computing is seeking a Principal Physical Implementation Engineer to provide technical leadership across its ASIC implementation activities.

This is an opportunity for an experienced Physical Design Engineer to take ownership of implementation quality, influence silicon development decisions and work across a broad range of engineering disciplines. The role combines hands-on technical expertise with responsibility for overseeing external implementation resources and shaping future internal capabilities.

The Role

As Principal Physical Implementation Engineer, you will be responsible for ensuring complex silicon designs are physically implementable, optimised and ready for tape-out. Working closely with internal design teams and external engineering partners, you will provide technical direction throughout the backend development process, from early implementation planning through to final silicon sign-off.

Key areas of responsibility include:

• Establishing the technical approach for physical implementation, ensuring design requirements and implementation expectations are clearly defined from the outset.

• Evaluating backend design deliverables, identifying potential issues across timing, power, area and physical implementation, and driving improvements where required.

• Providing technical leadership to outsourced implementation teams, reviewing their approach, challenging proposed solutions and maintaining confidence in implementation quality.

• Collaborating with RTL, architecture, verification and DFT engineers to address design decisions that influence physical implementation and overall silicon performance.

• Taking ownership of implementation readiness, including reviewing sign-off evidence and assessing outstanding technical risks ahead of tape-out.

• Contributing to integration decisions involving multiple dies, high-speed interconnects, memory and PHY components, with consideration for package and system-level constraints.

• Working with external technology partners to resolve implementation challenges and support successful silicon delivery.

• Identifying opportunities to improve backend processes, develop reusable methodologies and strengthen implementation infrastructure.

• Supporting the development of internal engineering expertise, with the opportunity to establish and lead a dedicated Physical Implementation team as the organisation grows.

What We’re Looking For

• A highly experienced ASIC Physical Design professional 

• Demonstrable involvement in taking complex digital silicon from implementation through to successful fabrication.

• Strong practical knowledge of backend design optimisation, including PPA, timing convergence, clock distribution and physical sign-off.

• Confidence working with timing constraints, implementation requirements and methodologies across sophisticated ASIC designs.

• Familiarity with leading industry EDA environments and the ability to independently assess implementation results and tool outputs.

• Experience navigating integration challenges involving embedded memories, third-party IP and high-speed interface components.

• Knowledge of low-power design implementation and associated power intent requirements.

• The ability to operate as a technical authority, providing direction to external engineering teams and making informed implementation decisions.

• Strong problem-solving capabilities and the confidence to operate within a developing silicon organisation where technical ownership is important.

Additional Experience That Would Be Beneficial

• Involvement in chiplet-based silicon or multi-die integration projects.

• Understanding of advanced packaging considerations and their influence on backend design decisions.

• Previous involvement in establishing or refining physical design flows and implementation standards.

• Exposure to collaboration with semiconductor foundries, EDA providers and external IP or memory vendors.

• Experience coaching engineers or taking responsibility for developing technical teams.

For more information on this role or others then please contact Jordan Browne at IC Resources for more information.