Senior / Staff Digital Design Engineer

Location: United Kingdom (Visa Sponsorship Available)
Salary: £65,000–£75,000 + Bonus + Equity + Excellent Benefits

A leading semiconductor company is seeking a Senior / Staff Digital Design Engineer to play a key role in the development of next-generation power management ICs (PMICs). This is an excellent opportunity to work on cutting-edge digital IC design, taking ownership of both existing IP and new digital designs from concept through to tape-out.

Working within a collaborative, multidisciplinary engineering team, you will contribute to advanced ASIC development, RTL design, low-power digital design, and digital IP architecture for innovative semiconductor products.

The Role

As a Senior / Staff Digital Design Engineer, you will lead digital core development across the complete ASIC design flow, from SystemVerilog RTL design through synthesis, timing closure, design-for-test (DFT), and final GDS delivery. You will collaborate closely with verification, analog, physical design, and system engineers to develop high-quality, low-power semiconductor solutions.

This position offers significant technical ownership and the opportunity to influence future digital architecture and IP development within a growing semiconductor business.

Key Responsibilities

• Lead the design and development of digital cores for advanced power management ICs (PMICs).
• Develop new digital IP while enhancing and maintaining existing IP blocks.
• Define and implement robust block-level digital architectures.
• Write high-quality SystemVerilog RTL for low-power ASIC designs.
• Work closely with Digital Verification Engineers to identify and resolve design issues before tape-out.
• Drive synthesis, timing closure, and Design for Test (DFT) activities.
• Coordinate physical implementation and backend design with external design partners.
• Apply low-power design methodologies, including clock gating and power optimisation techniques.
• Produce clear technical documentation and design specifications throughout the development cycle.

Requirements

• Degree in Electronic Engineering, Electrical Engineering or a related discipline (MEng preferred).
• Proven experience in Digital Design Engineering, ASIC Design, or RTL Design within the semiconductor industry.
• Strong expertise in SystemVerilog RTL design across the full digital design and synthesis flow.
• Experience with synchronous and asynchronous digital design techniques.
• Knowledge of low-power digital design methodologies.
• Experience with Cadence design and simulation tools or equivalent EDA tools.
• Scripting experience using Python, TCL, or CSH would be highly advantageous.
• Strong communication skills and the ability to collaborate across multidisciplinary engineering teams.

Package

• £65,000–£75,000 basic salary (dependent on experience)
• Performance-related bonus
• Equity opportunities
• Comprehensive benefits package
• UK Visa Sponsorship available for international candidates

If you’re an experienced Senior Digital Design Engineer, Staff Digital Design Engineer, ASIC Design Engineer, RTL Design Engineer, or Digital IC Design Engineer looking to work on industry-leading semiconductor technology, this is an outstanding opportunity to join an innovative engineering team developing the next generation of power management solutions.

To discuss this opportunity in confidence or apply, please contact Steph Hutchinson at IC Resources.