STA Engineer

A leading innovator in next-generation compute architectures, building high-performance, power-efficient CPU technology on the most advanced process nodes is looking for an experienced STA Engineer to join the team. You will contribute to timing closure for cutting-edge CPU IP developed in their world-class design group.

This is an opportunity to work with highly experienced engineers on complex CPU cores, helping to shape timing strategy, methodology and automation across several projects. If you want to work at the forefront of N3/N2 technology, this STA Engineer position offers genuine long-term growth and impact.

In this role, you will:

• Drive static timing analysis for advanced CPU blocks across multiple modes, corners and voltage domains
• Develop, refine and maintain timing constraints and timing-signoff practices to meet aggressive PPA targets
• Work closely with micro-architecture, RTL and physical design teams to debug timing paths, root-cause violations and propose practical solutions
• Automate flows and enhance STA-related infrastructure using scripting (TCL/Python/Perl)
• Evaluate timing approaches, methodologies and tool behaviour across new processes and libraries
• Partner with central methodology specialists to influence timing strategy across multiple design programmes

Ideal background

Candidates are likely to have:

• A degree in Electrical/Computer Engineering (or related discipline)
• Solid hands-on STA experience using tools such as PrimeTime or Tempus
• Familiarity with digital backend flows 
• Strong scripting ability to improve or automate timing flows

For more information, please contact Jordan Browne at IC Resources.