Design Verification Engineer

An opportunity has arisen for a Digital ASIC Verification Engineer to join a global semiconductor company designing and manufacturing advanced mixed-signal power ICs and sensors for a broad range of product applications. Situated in their Scotland design centre, the Verification Engineer will work as part of a growing design team developing digital control blocks and embedded processors for a brand-new generation of motor control ASICs.

This opportunity will allow an individual to contribute within the framework of a broader experienced analog, mixed-signal and digital team. We are looking for a motivated candidate that can leverage the group’s experience to begin quickly contributing to the success of the team.
 
The primary focus for the individual will be using cutting edge tools to verify state of the art products in my clients Model Based Design flow for digital signal processing applications. Knowledge of UVM, SystemVerilog assertions and Cadence verification tools is the key knowhow.

 Typical tasks for a sr. Digital Design Verification engineer include:

• Preparation of digital design test plan from requirements using Cadence
• Definition and creation of UVM-SV test environment, test plans, tests and functional coverage
• Verification of signal processing and control algorithms using Cadence and MathWorks tools
• Analysis of test results, improving test coverage and debug of unexpected design behaviour
• Preparation and/or leading of verification reviews
• Coordination of verification activities with abroad team members

 Please Note: You must have UK working rights for this role.

 For a detailed and confidential discussion please contact Rachel Mason at IC Resources.