Design Verification Engineer

Berkshire, England
Big-tech engineering. Small-team visibility. Great package.
Job ID: 493641

An opportunity has opened for Design Verification Engineers to join one of the most established and highly regarded semiconductor engineering teams in the UK.

The company develops sophisticated mixed-signal ICs used in some of the world’s best-known consumer technology products, giving you the chance to work on complex silicon that ultimately ships at huge scale.

They are hiring at multiple levels, so I’m keen to speak with experienced Verification Engineers through to Senior and Principal-level candidates.

The opportunity

You’ll work across the full ASIC/SoC verification lifecycle, with real ownership of the verification of complex digital subsystems and mixed-signal ICs.

Your work will include:

  • Developing SystemVerilog/UVM verification environments
  • Verification planning and test development
  • Constrained-random and coverage-driven verification
  • SVA / assertions
  • Functional and code coverage
  • RTL and testbench debugging
  • Verification methodology and infrastructure improvements
  • Working closely with design and architecture teams
  • Technical leadership and mentoring opportunities at senior levels

What they’re looking for

You’ll ideally have a background in ASIC, SoC or Digital IC Verification, with strong experience in:

SystemVerilog | UVM | SVA | Constrained Random Verification | Functional Coverage | RTL Debug

Experience with mixed-signal verification, formal verification, UPF/low-power verification, gate-level simulation or scripting would be particularly valuable.

Why consider it?

This is a strong option if you want technically challenging verification work without joining a tiny or highly speculative semiconductor business.

You’ll be joining an established global semiconductor company with complex products, experienced engineering teams, long-term career progression and a strong reputation for engineering culture.

📍 Edinburgh or Newbury, UK
🏠 Hybrid – typically 2+ days onsite
📈 Multiple levels available

If you’re a Design Verification Engineer, ASIC Verification Engineer or SoC Verification Engineer interested in hearing more, apply or get in touch with Steph Hutchinson  for a confidential conversation.