Digital Design Engineer

Want to work on the digital architecture behind a new generation of high-bandwidth, low-power AI interconnect technology?

I’m working with an advanced semiconductor company developing chiplet-based connectivity and memory fabric technology for AI infrastructure, using a highly differentiated approach to moving data over copper.

They are now looking for an experienced Digital IC Design Engineer to work on very high-speed digital circuits and interfaces.

What you’ll work on

• RTL design and microarchitecture for high-speed digital blocks
• Digital circuits for multi-Gigabit serial links, DDR and memory interfaces
• PCIe, USB4 and high-speed communication protocols
• Analog / digital interface definition alongside mixed-signal designers
• Logic synthesis, STA, CDC and lint
• IP and chip-level integration
• Verification and design sign-off
• Post-silicon bring-up, debug and characterisation
• Working closely with analog, verification and physical design teams

What they’re looking for

Ideally 5–10 years of digital IC / ASIC design experience, with strong knowledge of:

RTL Design | SystemVerilog / Verilog | ASIC Design | High-Speed Digital Design | SerDes | DDR | PCIe | USB4 | CDC | STA | Synthesis | Low-Power Design

Experience with multi-Gigabit transceivers, memory interfaces, mixed-signal ICs, Python scripting or Cadence tools would be particularly valuable.

Why consider it?

This is not generic RTL implementation.

You’ll work at the boundary between digital design, mixed-signal circuits and high-speed communications, helping turn system-level ideas into production silicon.

The technology is aimed directly at one of the biggest problems in AI hardware today: moving huge amounts of data with less power, lower latency and better scalability.

Location: Lausanne, Switzerland
Experience: 5–10+ years
Education: MSc / PhD in Electronics, Electrical Engineering, Communications or equivalent experience

If your background is in high-speed digital design, SerDes, DDR, PCIe or communications ASICs, I’d be keen to speak with you contact Steph Hutchinson for more details.