ASIC | Verification
+44 (0)118 907 0378
France | €65,000–€100,000 | SoC / NoC / Chiplets / CHI / UCIe
Want to work on the architecture behind some of the world’s most advanced SoCs and chiplet-based systems?
I’m working with a global semiconductor IP company whose technology is used by leading chip companies to build high-performance, power-efficient SoCs.
They are now looking for a Principal Hardware Architect / Cache Coherency Architect to help define and evolve next-generation cache-coherent Network-on-Chip IP.
Strong experience in:
Cache Coherency | SoC Architecture | NoC Architecture | Memory Hierarchies | CHI | UCIe | PCIe | Chiplets | Interconnect | RTL
You may currently be working as a:
SoC Architect, NoC Architect, Cache Coherency Architect, Principal Hardware Architect or senior ASIC Design Engineer moving into architecture.
This company operates right at the centre of one of the biggest challenges in modern semiconductor design: how increasingly complex processors, accelerators, memory systems and chiplets communicate efficiently.
You’ll work on commercially deployed IP used in advanced semiconductor products, while solving genuinely difficult problems in coherency, interconnect and system architecture.
Salary: €65,000–€100,000 base
Location: France
Eligibility: Existing EU work rights preferred
If you’re working in cache coherency, NoC, SoC architecture or chiplet interconnect, I’d be keen to speak with you contact Steph Hutchinson for more details.
1530 Arlington Business
Park, Berkshire.
RG7 4SA