Senior Design Verification Engineer

A major US semiconductor manufacturer is looking for several Senior Design Verification Engineers. You will be shaping the direction of cutting-edge IP for complex digital-AMS ASIC solutions.

You will be part of a global team tasked with the design and development of existing and brand-new products, taking a major hold in a niche market.

The desired applicant for the role of Senior Verification role will have strong knowledge in UVM verification and have worked within a mixed-signal environment.

Requirements:

• Expertise in UVM/System Verilog
• Experience working in a mixed signal environment 
• Proficiency in SystemVerilog and behavioural modelling of analog components for simulation within digital flows is highly desirable 
• Experience with real number modelling is highly desirable
• Fluent in English 

For more information on this role or others then please contact Jordan Browne for more information.